The present invention relates to a method and apparatus for planarizing a target object by means of CMP, i.e., Chemical Mechanical Polishing, especially in the field of semiconductor process. The semiconductor process includes various kinds of processes which are performed to manufacture a semiconductor device or a structure having wiring layers, electrodes, and the like to be connected to a semiconductor device, on a target substrate, such as a semiconductor wafer or an LCD substrate, by forming semiconductor layers, insulating layers, and conductive layers in predetermined patterns on the target substrate.
With an increase in the speed and integration level of semiconductor devices, planarization techniques for semiconductor wafers have become some of the most important techniques. This is because the accuracy of the planarization techniques has a great effect on the characteristics of semiconductor devices. For example, the planarization techniques need to have a high accuracy to ensure a designed depth of focus for lithography steps.
Among the planarization techniques, the CMP has attracted attention in recent years, in place of conventional techniques, such as etching-back of SOG (Spin On Glass), re-flowing of BPSG (Boron Phospho Silicate Glass) by a TEOS (tetraethyl orthosilicate)/O.sub.3 based gas. The CMP can present an excellent process accuracy in planarization of a wafer both locally and globally. Target objects to be planarized by the CMP include conductive and non-conductive layers.
FIGS. 8A to 8D are cross-sectional views showing steps in the order of a process of forming a wiring structure by means of a conventional CMP method. In these drawings, there are shown a semiconductor wafer 81, a plasma SiOx layer 82, a photoresist layer 83, wiring grooves 84, a barrier metal layer 85, and an Al alloy layer 86.
First, the plasma SiOx layer 82 having a thickness of 1.0 .mu.m is formed on the semiconductor wafer 81 by means of plasma CVD. Then, the photoresist layer 83 patterned by means of lithography is formed on the SiOx layer 82 (FIG. 8A).
The SiOx layer 82 is etched to form wiring grooves 84 therein, while the photoresist layer 83 is used as a mask. The photoresist layer 83 is then removed by means of O.sub.2 -plasma ashing (FIG. 8B).
To cover the inner surface of the wiring grooves 84, the barrier metal layer 85 consisting of TiN/Ti and having a thickness of 0.1 .mu.m is formed by means of sputtering. Then, the Al alloy layer 86 having a thickness of 1.0 .mu.m is formed on the barrier metal layer 85 to fill the wiring grooves 84, by means of high-temperature sputtering (FIG. 8C). At this time, the temperature of the sputtering is set at 450.degree. C.
That part of the Al alloy layer 86 outside the wiring grooves 84 is removed by a polishing treatment using a CMP method. As a result, a wiring structure formed of the wiring grooves 84 buried by the Al alloy layer 86 is completed (FIG. 8D). In the polishing treatment, its end point is determined as follows.
First, a polishing period of time is obtained to exactly correspond to a calculated value on the basis of a CMP rate derived from a test sample and the thickness of the Al alloy layer 86. Then, a process margin, such as 30% of the calculated period, is added thereto and the sum is set as an actual CMP period of time. The process margin is added in light of fluctuation in the process conditions, such as the thickness and shape of a target layer, and the like; mechanical fluctuation in the apparatus conditions, such as the surface condition of a polishing cloth, the pressure and relative speed between a polishing cloth and a target surface, the size of polishing powder particles, and the like; and chemical fluctuation in the apparatus conditions, such as the uniformity, volume and temperature of a polishing agent, and the like. In other words, the Al alloy layer 86 is over-polished not to allow a residue of the layer 86, i.e., the wiring material, to be left on the plasma SiOx layer 82, i.e., the insulating film, due to unevenness in the depth of the wiring grooves 84, the thickness of the Al alloy layer 86, the CMP rate, and the like.
However, there is a case where the process behavior itself is shifted toward an over-polishing, due to an independent effect or a synergetic effect of unevenness in the depth of the wiring grooves 84, the thickness of the Al alloy layer 86, the CMP rate, and the like. In this case, the above described method, which utilizes time administration, causes a dishing phenomenon in which the embedded material in the wiring grooves 84 becomes abnormally thin.
FIG. 9 is a view showing a dishing state after the Al alloy layer is polished by a conventional CMP method. The dishing degree Da may reach 20% to 35% of the depth Db of the wiring grooves 84 forming a buried pattern, due to a synergetic effect of unevenness in the above described factors. Where the thickness of wiring becomes unstably thinner than a designed value, problems arise in devices to be manufactured, such that their performance is degraded and their yield decreases, due to an increase in the wiring resistance, and an unevenness of the wiring resistance on the surface of one wafer or among wafers, and that their lifetime becomes short due to electro-migration. Generally, the dishing degree becomes higher as an area to be treated grows wider.
As a countermeasure against the dishing phenomenon, a hard polishing pad has been tested, but found to entail the following disadvantages. Specifically, a target surface to be treated by means of CMP has no ideal flatness as shown in FIG. 10A, but is waved as shown in FIG. 10B due to effects of a process and malflatness of a wafer. For this reason, it is preferable for the polishing surface of a polishing pad to extend along line La--La in FIG. 10B. However, the polishing surface of a hard polishing pad tends to be almost flat along line Lb--Lb in FIG. 10B. As a result, the thickness of polished wiring layers becomes uneven in the surface of a wafer, thereby lowering reliability of the wiring.
To reiterate, wiring decreases its reliability in either case of using a hard pad or a soft pad, because the polishing surface of the hard pad hardly follows the target surface, while the soft pad entails an increase in the dishing degree. In order to solve this problem, there has been proposed a polishing pad having a two-layer structure in which a hard pad is stacked on the surface of a soft resin. Although this structure is intended to solve the problem of a trade-off type by balancing the two members, disadvantages of the two members emerge to some extent in this structure, thereby resulting in a limit in solving the problem.
There has also been proposed a method of monitoring polished states in real time to detect an end point. However, since hardly any stable and effective method of detecting a CMP end point can be realized, it is inevitable to practically adopt the aforementioned method utilizing time administration.